A typical non-volatile memory cell consists of a source, a channel and a drain with a floating gate over the channel and a control gate over the floating gate. A wordline connected to the control gates of a plurality of memory cells provides the voltage necessary for the programming, reading, and erasure of the memory cells. During a programming step, the floating gate is charged with electrons, which increases the turn-on threshold voltage of the memory cell (i.e., it will remain non-conductive even when a read voltage, which is typically 5V, is applied to its control gate.) During an erasure step, electrons are removed from the floating gate to lower the threshold voltage. With a lower threshold voltage, the memory cell can be turned on to a conductive state when a read voltage is applied to the control gate.
A flash memory cell array is typically divided up into sectors and the erasure of the memory cell array is typically carried out by erasing one sector at a time. To erase a sector, a positive voltage is applied to the sources of all memory cells in the sector and a negative voltage is applied to all control gates through the wordlines. Because of the large number of cells in a sector, the band-to-band tunneling current is high. Therefore, this method of erasure requires a powerful voltage pump to provide the high voltage at the source. However, such a powerful voltage pump requires accompanying powerful circuitry that takes up substantial valuable chip space. Therefore, it would be desirable to have a flash memory design that does not require the use of such a powerful voltage pump.
In addition, flash memory cells sometimes suffer from the problem of over-erasure. Over-erasure occurs when, during the erasing step, too many electrons are removed from the floating gate, leaving a slightly positive charge that causes the memory cell to remain slightly turned-on even without any assertive voltage at its control gate. As a result, a small current may leak through the memory cell even when it is not addressed. A number of over-erased cells along a given bitline can cause an accumulation of leakage current that is sufficient to cause a false reading. Also, when the memory cells are over-erased, it is difficult to reprogram the cells successfully using hot electron programming. Over-erasure can be reduced by having a tight erase threshold voltage and having an even cell current distribution. However, due to the fact that the voltage supply has to be distributed to all memory cells in the sector during the erasure step, sometimes including the defective cells, a consistent erase threshold voltage and an even cell current is very difficult to achieve. Therefore, it would be desirable to reduce the number of over-erased memory cells by having a flash memory design that provides a tighter erase threshold voltage and a more even cell current distribution.
Moreover, if there is a defective row that has a path to ground, it will prevent the gate voltage from going negative, thereby rendering the whole sector inerasable. One current solution for this problem is to provide a redundant sector that will replace the deflective sector. However, a sector is a big block of memory cells and having multiple redundant replacement sectors would take up valuable chip space. It would be desirable to have a flash memory design that would allow the replacement of defective rows of memory cells with redundant rows of memory cells, thereby eliminating the need for the bulking redundant sectors.